Formal and Fault Tolerant Design

Software quality and reliability were verified for a long time at the post-implementation level (test, fault sce-nario ...). The design of embedded systems and digital circuits is more and more complex because of inte-gration density, heterogeneity. Now almost ¾ of the digital circuits contain at least one processor, that is, can execute software code. In other words, co-design is the most usual case and traditional verification by simu-lation is no more practical. Moreover, the increase in integration density comes with a decrease in the reliabil-ity of the components. So fault detection, diagnostics techniques, introspection are essential for defect toler-ance, fault tolerance and self repair of safety-critical systems. The use of a formal specification language is considered as the foundation of a real validation. What we would like to emphasize is that refinement (from an abstract model to the point where the system will be implemented) could be and should be formal too in order to ensure the traceability of requirements, to man-age such development projects and so to design fault-tolerant systems correct by proven construction. Such a thorough approach can be achieved by the automation or semi-automation of the refinement process. We have studied how to ensure the traceability of these requirements in a component-based approach. Re-liability, fault tolerance can be seen here as particular refinement steps. For instance, a given formal specifi-cation of a system/component may be refined by adding redundancy (data, computation, component) and be verified to be fault-tolerant w.r.t. some given fault scenarios. A self-repair component can be defined as the refinement of its original form enhanced with error detection. We describe in this paper the PCSI project (Zero Defect Systems) based on B Method, VHDL and PSL. The three modeling approaches can collaborate together and guarantee the codesign of embedded systems for which the requirements and the fault-tolerant aspects are taken into account for the beginning and formally verified all along the implementation process

Extended Model driven Architecture to B Method

International audienceModel Driven Architecture (MDA) design approach proposes to separate design into two stages: implementation independent stage then an implementation-dependent one. This improves the reusability, the reusability, the standability, the maintainability, etc. Here we show how MDA can be augmented using a formal refinement approach: B method. Doing so enables to gradually refine the development from the abstract specification to the executing implementation; furthermore it permits to prove the coherence between components in low levels even if they are implemented in different technologies

Multi-layered Spiking Neural Network with Target Timestamp Threshold Adaptation and STDP

Spiking neural networks (SNNs) are good candidates to produce ultra-energy-efficient hardware. However, the performance of these models is currently behind traditional methods. Introducing multi-layered SNNs is a promising way to reduce this gap. We propose in this paper a new threshold adaptation system which uses a timestamp objective at which neurons should fire. We show that our method leads to state-of-the-art classification rates on the MNIST dataset (98.60%) and the Faces/Motorbikes dataset (99.46%) with an unsupervised SNN followed by a linear SVM. We also investigate the sparsity level of the network by testing different inhibition policies and STDP rules

Unsupervised Visual Feature Learning with Spike-timing-dependent Plasticity: How Far are we from Traditional Feature Learning Approaches?

Spiking neural networks (SNNs) equipped with latency coding and spike-timing dependent plasticity rules offer an alternative to solve the data and energy bottlenecks of standard computer vision approaches: they can learn visual features without supervision and can be implemented by ultra-low power hardware architectures. However, their performance in image classification has never been evaluated on recent image datasets. In this paper, we compare SNNs to auto-encoders on three visual recognition datasets, and extend the use of SNNs to color images. The analysis of the results helps us identify some bottlenecks of SNNs: the limits of on-center/off-center coding, especially for color images, and the ineffectiveness of current inhibition mechanisms. These issues should be addressed to build effective SNNs for image recognition

Les graphes orientes ponderes : un outil pour l'etude de la terminaison et de la complexite dans les systemes de reecritures et en programmation logique

SIGLECNRS T Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

15. Le comportement douloureux de l’animal : entre symptômes et critères

Introduction L’étude du comportement animal est l’étude de l’interaction d’un individu avec ses congénères et avec son environnement, dans ses actions et réactions. Ainsi en est-il par exemple du comportement alimentaire, du comportement sexuel, des actions et réactions au sein même d’une espèce donnée dans un environnement donné. Nous allons parler ici d’un type particulier de comportement, le comportement douloureux. Mais il faut avouer d’emblée que le but de cette réflexion est de montrer ..

Formal Fault Tolerant Architecture

International audienc

Une approche analytique de la philosophie des droits de l anima

PARIS4-BU Serpente (751052129) / SudocSudocFranceF

N2S3, a Simulator for the Architecture Exploration of Neuromorphic Accelerators

International audienceWith the end in sight for Moore’s law and the end of Dennard’s scaling, the computing community has to find radically new computing architectures to fulfill the needs of Big Data and Cloud Computing while dealing with the energy consumptionlimits. It is well recognized now that artificial neural networks are such a promising architecture. The project we are involved in, in an interdisciplinary cooperation with teams form computer vision and from nanoelectronics, is to study the suitability of memristors to build a neuromorphic accelerator for computer vision